The present disclosure relates to dynamic random access memory (“DRAM”) and, more particularly, to memory cells and architectures with improved charging capabilities.
As shown in FIG. 1A, a conventional one-transistor one-capacitor (“1T1C”) DRAM cell is indicated generally by the reference numeral 10. The 1T1C DRAM cell 10 includes a transistor 12 in signal communication with a capacitor 13. A corresponding plot of memory cell voltage (“V_cell”) versus time is indicated generally by the reference numeral 15. During a Read operation, when a memory cell is Read and connected to the bitline (“BL”), the charges are shared between the cell and the BL or discharged to the BL, and subsequently the steady-state cell voltage, which is the same as the BL voltage, is equal after signal development to the voltage stored in the cell, V_cell (C_cell/(C_cell+C_bl)).
A voltage V_cell(1) is stored in the cell for a 1-data, while a voltage V_cell(0) of about 0 volts is stored in the cell for a 0-data. Here, assuming that the BL is precharged to 0 before the Read operation, other precharge voltages can be considered similarly. The ratio C_cell/(C_cell+C_bl) is known as the transfer ratio (“TR”), and it is less than 1. This means that there is a voltage drop in the cell during a Read operation. The gain of the cell measured by the ratio of the difference between V_cell(0) and V_cell(1) at sensing and before the Read operation is C_cell/(C_cell+C_bl), so Cell_Gain<1. In addition, a write-back operation is needed after the Read to restore the cell voltage to the pre-read level.
Thus, for a conventional 1T1C DRAM cell:
                              V_cell          ⁢          _inital          ⁢                                          ⁢                      (                          0              ,              1                        )                          =                ⁢                              V_cell            ⁢            _inital            ⁢                          (              1              )                                -                      V_cell            ⁢            _intial            ⁢                          (              0              )                                                              =                ⁢                  VBLH          -          0                                        =                ⁢        VBLH                                          V_cell          ⁢          _final          ⁢                                          ⁢                      (                          0              ,              1                        )                          =                ⁢                              V_cell            ⁢            _final            ⁢                          (              1              )                                -                      V_cell            ⁢            _final            ⁢                          (              0              )                                                              =                ⁢                              VBLH            ⁢                                                  ⁢                          C_cell              /                              (                                  C_cell                  +                  C_bl                                )                                              -          0                                        =                ⁢                  VBLH          ⁢                                          ⁢                      C_cell            /                          (                              C_cell                +                C_bl                            )                                                              Cell_Gain        =                ⁢                  V_cell          ⁢          _final          ⁢                                    (                              0                ,                1                            )                        /            V_cell                    ⁢          _intial          ⁢                      (                          0              ,              1                        )                                                  =                ⁢                  TR          ⁢                                          ⁢                      (                          Transfer              ⁢                                                          ⁢              Ratio                        )                                                  =                ⁢                              C_cell            /                          (                              C_cell                +                C_bl                            )                                <          1                    
Turning to FIG. 1B, a conventional two-transistor one-capacitor (“2T1C”) DRAM cell is indicated generally by the reference numeral 20. The 2T1C DRAM cell 20 includes a first transistor 22 in signal communication with a capacitor 23 and a second transistor 26. A corresponding plot of V_cell versus time is indicated generally by the reference numeral 25. During a Read operation, the cell is connected to the FET gate of the read device so as to develop a source to drain current on the BL for sensing, depending on the cell voltage being a 0 or High for 0- or 1-data. The cell voltage remains the same during the Read operation such that a write-back is not needed after the Read. The gain measured by the ratio of the differences between V_cell(0) and V_cell(1) at sensing and before the Read operation is 1, since the cell voltage remains the same regardless of the data being a 0 or 1, so Cell_Gain=1.
Thus, for a conventional 2T1C DRAM cell:
                              V_cell          ⁢          _inital          ⁢                                          ⁢                      (                          0              ,              1                        )                          =                ⁢                              V_cell            ⁢            _inital            ⁢                          (              1              )                                -                      V_cell            ⁢            _intial            ⁢                          (              0              )                                                              =                ⁢                  VBLH          -          0                                        =                ⁢        VBLH                                          V_cell          ⁢          _final          ⁢                                          ⁢                      (                          0              ,              1                        )                          =                ⁢                              V_cell            ⁢            _final            ⁢                          (              1              )                                -                      V_cell            ⁢            _final            ⁢                          (              0              )                                                              =                ⁢                  VBLH          -          0                                                  =                    ⁢          VBLH                ⁢                                                          Cell_Gain        =                ⁢                  V_cell          ⁢          _final          ⁢                                    (                              0                ,                1                            )                        /            V_cell                    ⁢          _intial          ⁢                      (                          0              ,              1                        )                                                  =                ⁢        1            
Accordingly, what is needed over a conventional 1T1C DRAM is a new memory cell that can (1) boost the Cell_Gain higher for the same amount of cell and bitline capacitance compared to the conventional 1T1C case, or (2) boost the Cell_Gain to greater than 1, which cannot be achieved with a conventional 1T1C DRAM.
In addition, what is needed over a conventional 2T1C DRAM is a new memory cell that can boost the Cell_Gain higher to always greater than 1 while achieving a signal about an order of magnitude greater than the conventional 2T1C case.